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| HIP6017B PRELIMINARY Data Sheet March 1999 File Number 4585 Advanced PWM and Dual Linear Power Control The HIP6017B provides the power control and protection for three output voltages in high-performance microprocessor and computer applications. The IC integrates a PWM controller, a linear regulator and a linear controller as well as the monitoring and protection functions into a single 28 lead SOIC package. The PWM controller regulates the microprocessor core voltage with a synchronous-rectified buck converter. The linear controller regulates power for the GTL bus and the linear regulator provides power for the clock driver circuits. The HIP6017B includes an Intel-compatible, TTL 5-input digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 2.1VDC to 3.5VDC in 0.1V increments and from 1.3VDC to 2.05VDC in 0.05V steps. The precision reference and voltage-mode control provide 1% static regulation. The linear regulator uses an internal pass device to provide 2.5V 2.5%. The linear controller drives an external N-Channel MOSFET to provide 1.5V 2.5%. The HIP6017B monitors all the output voltages. A single Power Good signal is issued when the core is within 10% of the DAC setting and the other levels are above their undervoltage levels. Additional built-in over-voltage protection for the core output uses the lower MOSFET to prevent output voltages above 115% of the DAC setting. The PWM overcurrent function monitors the output current by using the voltage drop across the upper MOSFET's rDS(ON), eliminating the need for a current sensing resistor. Features * Provides 3 Regulated Voltages - Microprocessor Core, Clock and GTL Power * Linear Controller Drives Either N-Channel MOSFETs or Bipolar Transistors * Operates from +3.3V, +5V and +12V Inputs * Simple Single-Loop PWM Control Design - Voltage-Mode Control * Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratios * Excellent Output Voltage Regulation - Core PWM Output: 1% Over Temperature - Other Outputs: 2.5% Over Temperature * TTL-Compatible 5-Bit Digital-to-Analog Core Output Voltage Selection - Wide Range - 1.3VDC to 3.5VDC - 0.1V Steps from 2.1VDC to 3.5VDC - 0.05V Steps from 1.3VDC to 2.05VDC * Power-Good Output Voltage Monitor * Microprocessor Core Voltage Protection Against Shorted MOSFET * Over-Voltage and Over-Current Fault Monitors - Does Not Require Extra Current Sensing Element, Uses MOSFET's rDS(ON) * Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator; Programmable from 50kHz to over 1MHz Pinout HIP6017B (SOIC) TOP VIEW NC 1 NC 2 VID4 3 VID3 4 VID2 5 VID1 6 VID0 7 PGOOD 8 GND2 9 V33 10 NC 11 SS 12 FAULT/RT 13 FB2 14 28 VCC 27 UGATE1 26 PHASE1 25 LGATE1 24 PGND 23 OCSET1 22 VSEN1 21 FB1 20 COMP1 19 FB3 18 DRIVE3 17 GND 16 VOUT2 15 VIN2 Applications * Full Motherboard Power Regulation for Computers * Low-Voltage Distributed Power Supplies Ordering Information PART NUMBER HIP6017BCB TEMP. RANGE (oC) 0 to 70 PACKAGE 28 Ld SOIC PKG. NO. M28.3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 Block Diagram DRIVE3 FB3 VSEN1 OCSET1 VCC V33 + + INHIBIT - 0.3V + LINEAR UNDERVOLTAGE 110% + POWER-ON 200A RESET (POR) 2 VIN2 + + 90% - PGOOD + - - + 1.26V OC2 LUV 115% - VOUT2 0.23A FB2 + - + - HIP6017B FAULT VIN2 + 2.5V + SOFTSTART AND FAULT LOGIC OV OC1 + UPPER DRIVE VCC UGATE1 - PHASE1 INHIBIT - + - + GATE CONTROL PWM VCC LGATE1 LOWER DRIVE PGND GND - + + 4.3V 11A TTL D/A CONVERTER (DAC) VCC ERROR AMP PWM COMP DACOUT OSCILLATOR GND2 4V SS VID4 VID0 VID2 VID1 VID3 FB1 COMP1 RT FIGURE 1. HIP6017B Simplified Power System Diagram +5VIN +3.3VIN VOUT2 LINEAR REGULATOR PWM1 CONTROLLER VOUT1 HIP6017B LINEAR CONTROLLER VOUT3 FIGURE 2. Typical Application +12VIN +5VIN LIN CIN VCC OCSET1 PGOOD VOUT2 FB2 COUT2 UGATE1 PHASE1 Q1 LOUT1 VOUT1 1.3V TO 3.5V POWERGOOD +3.3VIN VOUT2 2.5V VIN2 V33 LGATE1 Q3 VOUT3 1.5V DRIVE3 PGND Q2 CR1 COUT1 HIP6017B FB3 COUT3 VSEN1 FB1 COMP1 VID0 VID1 VID2 VID3 VID4 GND GND2 FAULT/RT SS CSS FIGURE 3. 3 HIP6017B Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V PGOOD, RT, FAULT, and GATE Voltage . . . GND - 0.3V to VCC + 0.3V Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 125oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER VCC SUPPLY CURRENT Nominal Supply POWER-ON RESET Rising VCC Threshold Falling VCC Threshold Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 SYMBOL TEST CONDITIONS MIN TYP MAX UNITS ICC UGATE1, DRIVE3, LGATE1, and VOUT4 Open - 10 - mA VOCSET = 4.5V VOCSET = 4.5V 8.6 8.2 2.45 - 2.55 500 1.25 10.4 10.2 2.65 - V V V mV V Rising VIN2 Under-Voltage Threshold VIN2 Under-Voltage Hysteresis Rising VOCSET1 Threshold OSCILLATOR Free Running Frequency Total Variation Ramp Amplitude REFERENCE AND DAC DAC(VID0-VID4) Input Low Voltage DAC(VID0-VID4) Input High Voltage DACOUT Voltage Accuracy Reference Voltage (Pin FB2 and FB3) LINEAR REGULATOR Regulation Under-Voltage Level Under-Voltage Hysteresis Over-Current Protection Over-Current Protection During Start-Up LINEAR CONTROLLER Regulation Under-Voltage Level Under-Voltage Hysteresis Output Drive Current IDRIVE3 VIN2 - VDRIVE3 > 0.6V FB3UV VSEN3 = DRIVE3, 0 < IDRIVE3 < 20mA FB3 Rising FB2UV 10mA < IVOUT2 < 150mA FB2 Rising VOSC RT = OPEN 6k < RT to GND < 200k RT = Open 185 -15 - 200 1.9 215 +15 - kHz % VP-P 2.0 -1.0 1.240 1.265 0.8 +1.0 1.290 V V % V -2.5 180 560 75 6 230 700 +2.5 87 - % % % mA mA -2.5 20 75 6 40 +2.5 87 - % % % mA 4 HIP6017B Electrical Specifications PARAMETER PWM CONTROLLER ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate PWM CONTROLLER GATE DRIVER Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink PROTECTION VOUT1 Over-Voltage Trip FAULT Sourcing Current OCSET1 Current Source Soft-Start Current Chip Shutdown Soft-Start Threshold POWER GOOD VOUT1 Upper Threshold VOUT1 Under-Voltage (Lower Threshold) VOUT1 Hysteresis (VSEN1/DACOUT) PGOOD Voltage Low VPGOOD VSEN1 Rising VSEN1 Rising Upper/Lower Threshold IPGOOD = -4mA 108 92 2 110 94 0.5 % % % V IOVP IOCSET ISS VSEN1 Rising VFAULT/RT = 10V VOCSET = 4.5VDC 112 10 170 115 14 200 11 118 230 1.0 % mA A A V IUGATE RUGATE ILGATE RLGATE VCC = 12V, VUGATE1 = 6V VUGATE1-PHASE1 = 1V VCC = 12V, VLGATE1 = 1V VLGATE1 = 1V 1 1.7 1 1.4 3.5 3.0 A A GBWP SR COMP = 10pF 88 15 6 dB MHz V/s Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Typical Performance Curves 100 CUGATE1 = CLGATE1 = CGATE VVCC = 12V, VIN = 5V 80 1000 RESISTANCE (k) RT PULLUP TO +12V ICC (mA) CGATE = 4800pF 60 CGATE = 3600pF 40 CGATE = 1500pF 100 10 RT PULLDOWN TO VSS 20 CGATE = 660pF 0 10 100 SWITCHING FREQUENCY (kHz) 1000 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) FIGURE 4. RT RESISTANCE vs FREQUENCY FIGURE 5. BIAS SUPPLY CURRENT vs FREQUENCY 5 HIP6017B Functional Pin Description VSEN1 (Pin 22) This pin is connected to the PWM converter's output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for over-voltage protection. UGATE1 (Pin 27) Connect UGATE pin to the PWM converter's upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. PGND (Pin 24) This is the power ground connection. Tie the synchronous PWM converter's lower MOSFET source to this pin. OCSET1 (Pin 23) Connect a resistor (ROCSET) from this pin to the drain of the respective upper MOSFET. ROCSET, an internal 200A current source (IOCSET), and the upper MOSFET onresistance (rDS(ON)) set the converter over-current (OC) trip point according to the following equation: I OCSET x R OCSET I PEAK = --------------------------------------------------r DS ( ON ) LGATE1 (Pin 25) Connect LGATE1 to the synchronous PWM converter's lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. VCC (Pin 28) Provide a 12V bias supply for the IC to this pin. This pin also provides the gate charge for all the MOSFETs controlled by the IC. An over-current trip cycles the soft-start function. Sustaining an over-current for 2 soft-start intervals shuts down the IC. Additionally, OCSET1 is an output for the inverted FAULT signal (FAULT). If a fault condition causes FAULT to go high, OCSET1 will be simultaneously pulled to ground though an internal MOS device (typical rDS(ON) = 100). FAULT/RT (Pin 13) This pin provides oscillator switching frequency adjustment. Placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: 5 x 10 Fs 200kHz + -------------------R T ( k ) 6 SS (Pin 12) Connect a capacitor from this pin to ground. This capacitor, along with an internal 11A current source, sets the softstart interval of the converter. Pulling this pin low with an open drain signal will shutdown the IC. (RT to GND) VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3) VID0-4 are the input pins to the 5-bit DAC. The states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the core converter output voltage. It also sets the core PGOOD and OVP thresholds. Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation: 4 x 10 Fs 200kHz - -------------------R T ( k ) 7 (RT to 12V) Nominally, this pin voltage is 1.26V, but is pulled to VCC in the event of an over-voltage or over-current condition. COMP1 and FB1 (Pins 20, and 21) COMP1 and FB1 are the available external pins of the PWM error amplifier. The FB1 pin is the inverting input of the error amplifier. Similarly, the COMP1 pin is the error amplifier output. These pins are used to compensate the voltagecontrol feedback loop of the PWM converter. DRIVE3 (Pin 18) Connect this pin to the gate of an external MOSFET or the base of an external bipolar NPN transistor. This pin provides the drive for the linear controller's pass transistor. FB3 (Pin 19) Connect this pin to a resistor divider to set the linear controller output voltage. GND and GND2 (Pins 17 and 9) Signal grounds for the IC. All voltage levels are measured with respect to these pins. VOUT2 (Pin 16) Output of the linear regulator. Supplies current up to 230mA. PGOOD (Pin 8) PGOOD is an open collector output used to indicate the status of the PWM converter output voltages. This pin is pulled low when the core output is not within 10% of the DACOUT reference voltage and the other outputs are below their under-voltage thresholds. The PGOOD output is open for `11111' VID code. See Table 1. FB2 (Pin 14) Connect this pin to a resistor divider to set the linear regulator output. VIN2 (Pin 15) VIN2 provides the input power to the integrated linear regulator. Connect this pin to the 3.3VDC supply. This pin is also monitored for UV events. PHASE1 (Pin 26) Connect the PHASE pin to the PWM converter's upper MOSFET source. This pin is used to monitor the voltage drop across the upper MOSFET for over-current protection. V33 (Pin 10) Connect this pin to the 3.3VDC supply. 6 HIP6017B Description Operation The HIP6017B monitors and precisely controls 3 output voltage levels (Refer to Figures 1, 2, and 3). It is designed for microprocessor computer applications with 3.3V and 5V power and 12V bias input from an ATX power supply. The IC has one PWM controller, a linear controller, and a linear regulator. The PWM controller (PWM) is designed to regulate the microprocessor core voltage (VOUT1). PWM controller drives 2 MOSFETs (Q1 and Q2) in a synchronousrectified buck converter configuration and regulates the core voltage to a level programmed by the 5-bit digital-to-analog converter (DAC). An integrated linear regulator supplies the 2.5V clock generator power (VOUT2). The linear controller drives an external MOSFET (Q3) to supply the GTL bus power (VOUT3). until each output reaches sufficient voltage to transfer control to the input reference clamp. If we consider the 2.0V output (VOUT1) in Figure 6, this time occurs at T2. During the interval between T2 and T3, the error amplifier reference ramps to the final value and the converter regulates the output to a voltage proportional to the SS pin voltage. At T3 the input clamp voltage exceeds the reference voltage and the output voltage is in regulation. PGOOD (2V/DIV) 0V SOFT-START (1V/DIV) Initialization The HIP6017B automatically initializes upon receipt of input power. By the time the soft-start (SS) voltage reaches 4V, the 3.3V input has to be high enough such that the two linear outputs (VOUT2, VOUT3) have exceeded their under-voltage threshold. A typical ATX supply meets this requirement. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias voltage (+12VIN) at the VCC pin and the 5V input voltage (+5VIN) at the OCSET1 pin. The normal level on OCSET1 is equal to +5VIN less a fixed voltage drop (see over-current protection). The POR function initiates soft-start operation after both input supply voltages exceed their POR thresholds. 0V VOUT2 ( = 2.5V) VOUT1 (DAC = 2V) OUTPUT VOLTAGES (0.5V/DIV) VOUT3 ( = 1.5V) 0V T0 T1 T2 T3 TIME T4 Soft-Start The POR function initiates the soft-start sequence. Initially, the voltage on the SS pin rapidly increases to approximately 1V (this minimizes the soft-start interval). Then an internal 11A current source charges an external capacitor (CSS) on the SS pin to 4V. The PWM error amplifier reference input (+ terminal) and output (COMP1 pin) are clamped to a level proportional to the SS pin voltage. As the SS pin voltage slews from 1V to 4V, the output clamp allows generation of PHASE pulses of increasing width that charge the output capacitor(s). After this initial stage, the reference input clamp slows the output voltage rate-of-rise and provides a smooth transition to the final set voltage. Additionally, both linear regulator's reference inputs are clamped to a voltage proportional to the SS pin voltage. This method provides a rapid and controlled output voltage rise. Figure 6 shows the soft-start sequence for the typical application. At T0 the SS voltage rapidly increases to approximately 1V. At T1, the SS pin and error amplifier output voltage reach the valley of the oscillator's triangle wave. The oscillator's triangular waveform is compared to the clamped error amplifier output voltage. As the SS pin voltage increases, the pulse-width on the PHASE pin increases. The interval of increasing pulse-width continues FIGURE 6. SOFT-START INTERVAL The remaining outputs are also programmed to follow the SS pin voltage. Each linear output (VOUT2 and VOUT3) initially follows a ramp similar to that of the PWM output. When each output reaches sufficient voltage the input reference clamp slows the rate of output voltage rise. The PGOOD signal toggles `high' when all output voltage levels have exceeded their under-voltage levels. See the Soft-Start Interval section under Applications Guidelines for a procedure to determine the soft-start interval. Fault Protection All three outputs are monitored and protected against extreme overload. A sustained overload on any linear regulator output or an over-voltage on the PWM output disables all converters and drives the FAULT/RT pin to VCC. Figure 7 shows a simplified schematic of the fault logic. An over-voltage detected on VSEN1 immediately sets the fault latch. A sequence of three over-current fault signals also sets the fault latch. A comparator indicates when CSS is fully charged (UP signal), such that an under-voltage event on either linear output (FB2 or FB3) is ignored until after the 7 HIP6017B LUV OVER CURRENT LATCH OC1 SQ R 0.15V + S COUNTER R SS 4V + UP POR OV FAULT LATCH SQ FAULT/RT 10V 0V COUNT =1 SOFT-START 4V 2V 0V OVERLOAD APPLIED COUNT =2 COUNT =3 R FAULT FAULT REPORTED VCC INHIBIT - inductor current increases to trip the over-current comparator. Again, this inhibits all outputs, but the soft-start voltage continues increasing to 4V before discharging. The counter increments to 2. The soft-start cycle repeats at T3 and trips the over-current comparator. The SS pin voltage increases to 4V at T4 and the counter increments to 3. This sets the fault latch to disable the converter. The fault is reported on the FAULT/RT pin. FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC soft-start interval (T4 in Figure 6). At start-up, this allows VOUT2 and VOUT3 to slew up without generating a fault. Cycling the bias input voltage (+12VIN on the VCC pin) off then on resets the counter and the fault latch. Over-Voltage Protection During operation, a short on the upper PWM MOSFET (Q1) causes VOUT1 to increase. When the output exceeds the over-voltage threshold of 115% (typical) of DACOUT, the over-voltage comparator trips to set the fault latch and turns Q2 on as required in order to regulate VOUT1 to 1.15 x DACOUT. This blows the input fuse and reduces VOUT1. The fault latch raises the FAULT/RT pin close to VCC potential. A separate over-voltage circuit provides protection during the initial application of power. For voltages on the VCC pin below the power-on reset (and above ~4V), VOUT1 is monitored for voltages exceeding 1.26V. Should VSEN1 exceed this level, the lower MOSFET (Q2) is driven on as needed to regulate VOUT1 to 1.26V. INDUCTOR CURRENT 0A T0 T1 T2 TIME T3 T4 FIGURE 8. OVER-CURRENT OPERATION Over-Current Protection All outputs are protected against excessive over-currents. The PWM controller uses the upper MOSFET's onresistance, rDS(ON) to monitor the current for protection against shorted outputs. The linear regulator monitors the current of the integrated power device and signals an overcurrent condition for currents in excess of 230mA. Additionally, both the linear regulator and the linear controller monitor FB2 and FB3 for under-voltage to protect against excessive currents. Figures 8 and 9 illustrate the over-current protection with an overload on OUT1. The overload is applied at T0 and the current increases through the output inductor (LOUT1). At time T1, the OVER-CURRENT1 comparator trips when the voltage across Q1 (ID x rDS(ON)) exceeds the level programmed by ROCSET. This inhibits all outputs, discharges the soft-start capacitor (CSS) with a 11mA current sink, and increments the counter. CSS recharges at T2 and initiates a soft-start cycle with the error amplifiers clamped by soft-start. With OUT1 still overloaded, the The linear regulator operates in the same way as PWM1 to over-current faults. Additionally, the linear regulator and linear controller monitor the feedback pins for an undervoltage. Should excessive currents cause FB2 or FB3 to fall below the linear under-voltage threshold, the LUV signal sets the over-current latch if CSS is fully charged. Blanking the LUV signal during the CSS charge interval allows the linear outputs to build above the under-voltage threshold during normal start-up. Cycling the bias input power off then on resets the counter and the fault latch. Resistor ROCSET1 programs the over-current trip level for the PWM converter. As shown in Figure 9, the internal 200A current sink develops a voltage across ROCSET (VSET) that is referenced to VIN. The DRIVE signal enables the over-current comparator (OVER-CURRENT1). When the voltage across the upper MOSFET (VDS(ON)) exceeds VSET, the overcurrent comparator trips to set the over-current latch. Both VSET and VDS are referenced to VIN and a small capacitor across ROCSET helps VOCSET track the variations of VIN due to MOSFET switching. The over-current function will trip at a peak inductor current (IPEAK) determined by: I OCSET x R OCSET I PEAK = --------------------------------------------------r DS ( ON ) The OC trip point varies with MOSFET's temperature. To avoid over-current tripping in the normal operating load 8 HIP6017B range, determine the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for IPEAK > IOUT(MAX) + (I)/2, where I is the output inductor ripple current. For an equation for the output inductor ripple current see the section under component guidelines titled `Output Inductor Selection'. OVER-CURRENT TRIP: VDS > VSET (iD x rDS(ON) > IOCSET x ROCSET) OCSET IOCSET 200A VCC + DRIVE OC1 + UGATE PHASE VCC GATE CONTROL LGATE PGND VPHASE = VIN - VDS VOCSET = VIN - VSET VDS ROCSET iD VIN = +5V programmed by the soft-start capacitor, CSS. Programming a faster soft-start interval increases the peak surge current. The peak surge current occurs during the initial output voltage rise to 80% of the set value. Shutdown The PWM output does not switch until the soft-start voltage (VSS) exceeds the oscillator's valley voltage. Additionally, the reference on each linear's amplifier is clamped to the softstart voltage. Holding the SS pin low with an open drain or collector signal turns off all three regulators. The `11111' VID code resulting in an INHIBIT as shown in Table 1 also shuts down the IC. TABLE 1. VOUT1 VOLTAGE PROGRAM PIN NAME NOMINAL OUT1 VOLTAGE DACOUT 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 INHIBIT 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 VSET + VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 OVERCURRENT1 PWM HIP6017B - FIGURE 9. OVER-CURRENT DETECTION OUT1 Voltage Program The output voltage of the PWM converter is programmed to discrete levels between 1.3VDC and 3.5VDC. This output is designed to supply the microprocessor core voltage. The voltage identification (VID) pins program an internal voltage reference (DACOUT) through a TTL-compatible 5-bit digital-to-analog converter. The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the different combinations of connections on the VID pins. The VID pins can be left open for a logic 1 input, because they are internally pulled up to +5V by a 10A (typically) current source. Changing the VID inputs during operation is not recommended. The sudden change in the resulting reference voltage could toggle the PGOOD signal and exercise the over-voltage protection. The `11111' VID pin combination resulting in an INHIBIT disables the IC and the open-collector at the PGOOD pin. Application Guidelines Soft-Start Interval Initially, the soft-start function clamps the error amplifier's output of the PWM converter. After the output voltage increases to approximately 80% of the set value, the reference input of the error amplifier is clamped to a voltage proportional to the SS pin voltage. Both linear outputs follow a similar start-up sequence. The resulting output voltage sequence is shown in Figure 6. The soft-start function controls the output voltage rate of rise to limit the current surge at start-up. The soft-start interval is NOTE: 0 = connected to GND or VSS, 1 = open or connected to 5V through pull-up resistors. 9 HIP6017B Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying the full load current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET (and/or parallel Schottky diode). Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. Contact Intersil for evaluation board drawings of the component placement and printed circuit board. There are two sets of critical components in a DC-DC converter using a HIP6017B controller. The power components are the most critical because they switch large amounts of energy. The critical small signal components connect to sensitive nodes or supply critical bypassing current. The power components should be placed first. Locate the input capacitors close to the power switches. Minimize the length of the connections between the input capacitors and the power switches. Locate the output inductor and output capacitors between the MOSFETs and the load. Locate the PWM controller close to the MOSFETs. The critical small signal components include the bypass capacitor for VCC and the soft-start capacitor, CSS. Locate these components close to their connecting pins on the control IC. Minimize any leakage current paths from SS node because the internal current source is only 11A. A multi-layer printed circuit board is recommended. Figure 10 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the control IC to the MOSFET gate and source should be sized to carry 1A currents. The traces for OUT2 need only be sized for 0.2A. Locate COUT2 close to the HIP6017B IC. +5VIN +3.3VIN +12V CVCC VCC GND VIN2 OCSET1 VOUT3 LOAD Q3 UGATE1 Q1 DRIVE3 PHASE1 Q2 HIP6018 VOUT2 LGATE1 SS PGND COCSET1 ROCSET1 LOUT1 VOUT1 LOAD CIN COUT1 CR1 VOUT2 LOAD COUT2 CSS KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA CONNECTION TO GROUND PLANE FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS PWM Controller Feedback Compensation Both PWM controllers use voltage-mode control for output regulation. This section highlights the design consideration for a voltage-mode controller. Apply the methods and considerations to both PWM controllers. Figure 11 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage is regulated to the reference voltage level. The reference voltage level is the DAC output voltage for the PWM controller. The error amplifier output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC gain and the output filter, with a double pole break frequency at FLC and a zero at FESR. The DC gain of the modulator is simply the input voltage, VIN, divided by the peak-to-peak oscillator voltage, VOSC . 10 HIP6017B VIN OSC PWM COMP DRIVER LO DRIVER PHASE CO ESR (PARASITIC) ZFB VE/A VOUT VOSC + ERROR AMP + ZIN REFERENCE Figure 12 shows an asymptotic plot of the DC-DC converter's gain vs frequency. The actual modulator gain has a peak due to the high Q factor of the output filter at FLC, which is not shown in Figure 12. Using the above guidelines should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The closed loop gain is constructed on the log-log graph of Figure 12 by adding the modulator gain (in dB) to the compensation gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. 100 80 60 GAIN (dB) 40 20 0 -20 20LOG (R2/R1) MODULATOR GAIN OPEN LOOP ERROR AMP GAIN FZ1 FZ2 FP1 FP2 DETAILED FEEDBACK COMPENSATION ZFB C2 C1 R2 C3 R1 COMP ZIN R3 VOUT + 20LOG (VIN/VOSC) COMPENSATION GAIN FLC CLOSED LOOP GAIN 1M 10M FB HIP6017B REFERENCE -40 -60 FESR 10K 100K 10 100 1K FIGURE 11. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN FREQUENCY (Hz) Modulator Break Frequency Equations 1 F LC = --------------------------------------2 x L O x C O 1 F ESR = ---------------------------------------2 x ESR x C O FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN The compensation network consists of the error amplifier internal to the HIP6017B and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with an acceptable 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network's poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 11. Use these guidelines for locating the poles and zeros of the compensation network: 1. 2. 3. 4. 5. 6. 7. Pick Gain (R2/R1) for desired converter bandwidth Place 1ST Zero Below Filter's Double Pole (~75% FLC) Place 2ND Zero at Filter's Double Pole Place 1ST Pole at the ESR Zero Place 2ND Pole at Half the Switching Frequency Check Gain against Error Amplifier's Open-Loop Gain Estimate Phase Margin - Repeat if Necessary 1 F P1 = -----------------------------------------------------C1 x C2 2 x R 2 x --------------------- C1 + C2 1 F P2 = ----------------------------------2 x R 3 x C3 The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth loop. A stable control loop has a 0dB gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. Component Selection Guidelines Output Capacitor Selection The output capacitors for each output have unique requirements. In general the output capacitors should be selected to meet the dynamic regulation requirements. Additionally, the PWM converters require an output capacitor to filter the current ripple. The linear regulator is internally compensated and requires an output capacitor that meets the stability requirements. The load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demands. PWM Output Capacitors Modern microprocessors produce transient load rates above 10A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and ESL (effective series inductance) parameters rather than actual capacitance. Compensation Break Frequency Equations 1 F Z1 = ----------------------------------2 x R 2 x C1 1 F Z2 = -----------------------------------------------------2 x ( R1 + R3 ) x C3 11 HIP6017B High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching regulator applications for the bulk capacitors. The bulk capacitor's ESR determines the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select suitable components. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. For a given transient load magnitude, the output voltage transient response due to the output capacitor characteristics can be approximated by the following equation: dI TRAN V TRAN = ESL x -------------------- + ESR x I TRAN dt Output Inductor Selection The PWM converter requires an output inductor. The output inductor is selected to meet the output voltage ripple requirements and sets the converter's response time to a load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: V IN - V OUT V OUT I = ------------------------------- x --------------V IN FS x LO V OUT = I x ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the HIP6017B will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the post-transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O x I TRAN t RISE = ------------------------------V IN - V OUT L O x I TRAN t FALL = -----------------------------V OUT Linear Output Capacitors The output capacitors for the linear regulator and the linear controller provide dynamic load current. The linear controller uses dominant pole compensation integrated in the error amplifier and is insensitive to output capacitor selection. Capacitor, COUT3 should be selected for transient load regulation. The output capacitor for the linear regulator provides loop stability. The linear regulator (OUT2) requires an output capacitor characteristic shown in Figure 13. The upper line plots the 45 phase margin with 150mA load and the lower line is the 45 phase margin limit with a 10mA load. Select a COUT2 capacitor with characteristic between the two limits. 0.7 0.6 0.5 ESR () 0.4 0.3 0.2 0.1 10 100 CAPACITANCE (F) 1000 LE N AB IO ST RAT E OP where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load, and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use ceramic capacitance for the high frequency decoupling and bulk capacitors to FIGURE 13. COUT2 OUTPUT CAPACITOR 12 HIP6017B supply the RMS current. Small ceramic capacitors should be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. The rDS(ON) is different for the two previous equations even if the type device is used for both. This is because the gate drive applied to the upper MOSFET is different than the lower MOSFET. Figure 14 shows the gate drive where the upper gate-to-source voltage is approximately VCC less the input supply. For +5V main power and +12VDC for the bias, the gate-to-source voltage of Q1 is 7V. The lower gate drive voltage is +12VDC. A logic-level MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC . +5V OR LESS +12V VCC Transistor Selection/Considerations The HIP6017B requires 3 external transistors. Two N-Channel MOSFETs are used in the synchronous-rectified buck topology of the PWM converter. The linear controller drives either a MOSFET or a NPN bipolar as a pass transistor. These transistors should be selected based upon rDS(ON) , gate supply requirements, and thermal management requirements. HIP6017B UGATE PHASE Q1 NOTE: VGS VCC -5V Q2 CR1 NOTE: VGS VCC - + LGATE PGND GND PWM1 MOSFET Selection and Considerations In high-current PWM applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty factor (see the equations below). The conduction loss is the only component of power dissipation for the lower MOSFET. Only the upper MOSFET has switching losses, since the lower device turns on into near zero voltage. The equations below assume linear voltage-current transitions and do not model power loss due to the reverserecovery of the lower MOSFET's body diode. The gatecharge losses are proportional to the switching frequency (FS) and are dissipated by the HIP6017B, thus not contributing to the MOSFETs' temperature rise. However, large gate charge increases the switching interval, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. I O x r DS ( ON ) x V OUT I O x V IN x t SW x F S P UPPER = ----------------------------------------------------------- + ---------------------------------------------------V IN 2 I O x r DS ( ON ) x ( V IN - V OUT ) P LOWER = -------------------------------------------------------------------------------V IN 2 2 FIGURE 14. OUTPUT GATE DRIVERS Rectifier CR1 is a clamp that catches the negative inductor voltage swing during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency might drop one or two percent as a result. The diode's rated reverse breakdown voltage must be greater than twice the maximum input voltage. Linear Controller Transistor Selection The main criteria for selection of transistors for the linear regulators is package selection for efficient removal of heat. The power dissipated in a linear regulator is: P LINEAR = I O x ( V IN - V OUT ) Select a package and heatsink that maintains the junction temperature below the maximum rating while operating at the highest expected ambient temperature. When selecting bipolar NPN transistors for use with the linear controllers, insure the current gain at the given operating VCE is sufficiently large to provide the desired output load current when the base is fed with the minimum driver output current. 13 HIP6017B HIP6017B DC-DC Converter Application Circuit Figure 15 shows an application circuit of a power supply for a microprocessor computer system. The power supply provides the microprocessor core voltage (VOUT1), the GTL bus voltage (VOUT3) and clock generator voltage (VOUT2) from +3.3VDC, +5VDC and +12VDC. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note AN9800. Also see Intersil' web page (http://www.semi.intersil.Intersilcom) or Intersil AnswerFAX (407-724-7800) for the latest information. +12VIN F1 +5VIN 15A GND L1 1H C1-4 4x1000F + C16 1F C18 VCC 28 GND2 23 9 8 OCSET1 1.3K POWERGOOD PGOOD 1000pF R2 C15 1F NC NC 1 2 27 26 UGATE1 PHASE1 Q1 HUF76139S3S L3 2.9H VOUT1 (1.3 TO 3.5V) 25 24 +3.3VIN + C19 1000F VIN2 V33 NC LGATE1 PGND Q2 HUF76139S3S C24-36 + 7x1000F R4 4.99K HIP6017B 15 10 11 20 22 21 VSEN1 FB1 R8 2.21K COMP1 C41 10pF C42 R10 150K R9 732K VID0 VID1 VID2 VID3 VID4 C40 0.68F Q3 HUF75307D3S VOUT3 (1.5V) + C43-46 4x1000F R13 10K + C47 270F R11 1.87K R12 10K DRIVE3 FB3 7 18 19 6 5 4 VID0 VID1 VID2 VID3 VID4 SS C48 0.039F 0.01F VOUT2 FB2 R14 10K 3 16 12 14 13 FAULT/RT 17 VOUT2 (2.5V) GND FIGURE 15. APPLICATION CIRCUIT 14 HIP6017B Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 B C D E A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 15 HIP6017B All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 16 |
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